In semiconductor device manufacturing technology, when a design rule is decreased, pattern density increases, and formation of a precise pattern becomes an issue. Since it is difficult to achieve precise patterning in a fine process with a small design rule, and particularly, patterning in an active process, a delicate pattern is obtained through artificial pattern handling, such as optical proximity correction (OPC).
For purposes set out below, a technique of inserting a dummy pattern between main patterns is used. First, this technique is used to prevent the sizes of the main patterns from varying, according to their density, in a photolithography process or an etching process, and to achieve a fine pattern. Further, this technique is used to prevent variations in planarization according to the densities of the main patterns in a subsequent planarization process.
In cases where a dummy pattern is inserted into a boundary area between wells formed in a semiconductor substrate, a salicide may be formed over the upper surface of the dummy pattern by a salicide process. The formed salicide may generate leakage current. Since leakage current greatly influences characteristics of a semiconductor device, the dummy pattern cannot be formed over the upper surface of the boundary area between the wells.
FIG. 1 is a plan view illustrating a related semiconductor device, and FIG. 2 is a longitudinal-sectional view taken along the line C-C′ of the semiconductor device of FIG. 1.
With reference to FIGS. 1 and 2, the semiconductor device includes a semiconductor substrate 1, an N-well 10 formed in one region of the semiconductor substrate 1, a P-well 20 formed in another region of the semiconductor substrate 1, an isolation region 30, active regions 32 and 34, electrodes 40a and 40b, and contacts 50a and 50b. The contacts 50a and 50b are formed in the active regions 32 and 34. The electrodes 40a and 40b are formed over the upper surfaces of the contacts 50a and 50b, and the contacts 50a and 50b are electrically connected to the electrodes 40a and 40b. 
In cases where exposure and etching processes are carried out without a dummy pattern formed in a boundary area A between the wells 10 and 20, the size of the first active region 32 and the size of the second active region 34 may not be equal. Further, in cases where a planarization process is carried out without a dummy pattern formed in the boundary area A, a difference in the degree of planarization may be generated and thus dishing may occur.
FIG. 3 illustrates a leakage current generated when a dummy active pattern 50 is inserted into a boundary area (the portion “A”) between the wells 10 and 20, shown in FIG. 2. With reference to FIG. 3, in a case where the dummy active pattern 50 is formed in the boundary area A, a salicide 60 may be formed over the upper surface of the dummy active pattern 50 through a salicide process, which will be carried out later.
To operate the semiconductor device, voltage Vdd of a first power supply is supplied to the N-well 10 through the first electrode 40a and the first contact 50a, and voltage Vss of a second power supply is supplied to the P-well 20 through the second electrode 40b and the second contact 50b. 
A current path 70, as shown in FIG. 3, is formed between the first power supply and the second power supply by the salicide 60 formed over the upper surface of the dummy active pattern 50, and thus a leakage current may be generated.
Due to the leakage current generated when the dummy active pattern is formed over the upper surface of the boundary area A between the wells 10 and 20, the technique of inserting a dummy pattern between main patterns is not used in the boundary area A.